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About the job role
This role is located at the Caswell site. This is a full-time role. This is a temporary position, the minimum period of employment is 6 months and maximum is 12 months. A monthly salary will be paid, based on a 37.5 hour, 5 day working week.
- To work as part of the Indium phosphide optoelectronic chip design team, evaluating performance of prototype chips
- Role will include laboratory work, measuring performance of chips, collecting and analysing data and presenting results to the design team
- Depending on the suitability of the candidate some chip design and modelling tasks may also be involved
Key responsibilities
- Use a range of measurement techniques to assess advanced optoelectronic components including both DC and AC measurements.
- Where necessary automate measurements to increase throughput and speed of data gathering.
- Where necessary use computational modelling tools to further enhance understanding of device performance.
- Interact with wider R&D teams at Caswell to present the results of measurements or modelling activities.
Minimum requirements
- Studying at undergraduate level or above: physics or engineering related subjects
- Sound basic knowledge of optics, laser and semiconductor physics
- Knowledge of optical fibre transmission systems useful but not essential
- Experience of laboratory work, at undergraduate level or above
- Demonstrated ability to plan experiments, design and build test equipment, carry out measurements, record results and analyse data (programming skills useful but not essential)
- Demonstrated good communications skills – report writing, presentations, team working
- Familiarity with Python and Microsoft Excel/Powerpoint desirable
Personal requirements
The candidate shall be a highly motivated individual, able to communicate clearly both verbally and in writing and able to work well in complex and diverse team environment.
The candidate will need to work closely with other members of the laser design and integrated laser-modulator team, and from time to time with members of the wider chip R&D community.
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